GaN devices are expected to be widely adopted for power switches as production costs are reduced, for example, by fabrication of lateral GaN transistors on lower cost silicon substrates (GaN-on-Si die). Lateral GaN power transistors offer low on-resistance Ron and high current capability per unit active area of the device.
For example, lateral GaN High Electron Mobility Transistors (HEMTs) comprise a GaN heterolayer structure comprising a layer of GaN and an overlying layer of Aluminum Gallium Nitride (AlGaN). The GaN/AlGaN heterostructure provides a two-dimensional Electron Gas (2DEG) active layer. The GaN semiconductor layers are epitaxially grown on the underlying native silicon substrate (“growth substrate”). Since there is a lattice mismatch between the GaN semiconductor layers and the silicon surface, the stack of epitaxial layers (epi-layer stack) typically comprises one or more intermediate layers, which may be referred to as transition layers or buffer layers, underlying the GaN/AlGaN heterostructure layers.
Silicon growth substrates offer lower cost fabrication relative to conventional growth substrates for GaN devices, such as, silicon carbide or sapphire. In particular, silicon substrates are available as large diameter, low cost wafers. It is desirable to increase wafer scale processing for GaN-on-Silicon structures to enable use of at least 8 inch or 12 inch silicon wafers.
However, the lattice mismatch between the GaN semiconductor layers and the silicon surface tends to cause significant interlayer stresses/strains and wafer bowing when using large scale wafers. A thinner epi-layer stack thickness, e.g. ˜2 μm, helps to reduce stresses and wafer bowing that is caused by the GaN/Si lattice mismatch, so that use of larger diameter wafers for larger scale fabrication becomes feasible. However, for high voltage and high current devices, the use of a thicker GaN epi-layer stack, e.g. ˜6 μm, may be preferred to provide increased breakdown voltage.
The lattice mismatch and the resulting interlayer stresses/strains between the GaN epi-layers and the silicon substrate introduces defects, such as misfit dislocations, which can potentially lead to cracking during fabrication and subsequent defect related reliability issues.
One significant issue is cracking or propagation of defects in the GaN epi-layers during wafer dicing to separate individual die. For example, it has been observed that wafer dicing using conventional mechanical sawing, i.e. blade dicing with a diamond saw, can cause dicing damage that seeds cracks in the GaN epi-layers. If these cracks are not detected in final test, the cracks can subsequently propagate into active areas of the device and cause reliability issues. Laser ablation or laser grooving is another well-established approach to die singulation, which avoids the mechanical damage and debris caused by wafer sawing with a blade. Laser grooving may be used instead of wafer sawing, or in combination with conventional wafer sawing. However, it has been observed that laser grooving also creates surface damage and/or defects in the region of the substrate/GaN epi-layer interface. A subsequent etching or surface cleaning step may be required to mitigate this damage.
Other methods for wafer dicing include plasma dicing, Stealth Dicing (SD) and other methods using laser induced cleaving or splitting. Plasma dicing uses reactive ion etching or other form of dry etching, to cut a trench and remove material from the dicing street. Stealth dicing uses high power laser pulses, which create microscopic sub-surface damage to initiate controlled cleaving or splitting of the substrate wafer along the laser defined scribe line.
“Stealth Dicing” is disclosed for example in U.S. Pat. No. 6,992,026; https://jp.hamamatsu.com/sd/SD_MENU_Comparison_eg_html; and http://www.hamamatsu.com/eu/en/technology/innovation/sd/index.html. For some substrate materials, the latter approach has been reported to reduce damage and debris and eliminate the need for a cleaning or etching to remove dicing debris or laser damage after dicing, e.g. when cutting substrate materials such as silicon and glass. United States patent publication No. US 2015/0123264 to Napetschnig et al. (Infineon), discusses limitations of plasma dicing and discloses that modern wafer dicing methods, such as plasma dicing offer advantages for some materials, but may not be suitable for cutting through other materials, e.g. thick metal layers such as back-side contact metallization layers. United States patent publication No. US2012/0292642 to Urata et al. entitled “Functional Element and Manufacturing Method of the Same” makes reference to several prior art patent documents disclosing methods for cleaving or splitting semiconductor substrates. For example, this reference discloses a method of splitting a wafer comprising a GaN HEMT on a silicon carbide substrate using a property altering laser light, i.e. having short pulses picosecond or femtosecond pulsed laser, to form subsurface regions that are easier to split and/or to laser cut V-grooves as scribe lines to facilitate controlled splitting or cleaving of a sapphire or silicon carbide wafer. However, for GaN-on-Si die, stealth dicing or other methods for inducing cleaving of the GaN epi-layers would lead to cracking and damage of the GaN-epilayers.
Thus, it is apparent that there is a range of known methods available for die singulation including conventional mechanical cutting or sawing, laser ablation or laser grooving, plasma dicing or dry etching of grooves or trenches, and or more recently introduced laser induced cleaving/splitting techniques. However, none of the above mentioned references address issues of cracking or delamination of the GaN epi-layers during wafer dicing for singulation of large area GaN-on-Si die comprising high voltage/high current GaN power transistors.
In contrast, the issue of crack formation and propagation in dielectric layers at corners or edges of a die during wafer dicing is well recognized. For example, issues of poor yield and reliability caused by poor mechanical properties of low k dielectrics which can lead to dicing induced damage and may cause cracking of dielectric layers and delamination of metal and dielectric layers is discussed, for example, in United States Patent Application publication No. US 2015/0311162 A1, to Chen (TSMC) entitled “Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof”; U.S. Pat. No. 8,354,734 B2 to Wang (TSMC) entitled “Semiconductor Device with Crack Prevention Ring”; U.S. Pat. No. 9,105,706 B2 to Otsuka (Fujitsu), entitled “Semiconductor Device Fabrication Method Capable Of Scribing Chips With High Yield”; and U.S. Pat. No. 8,652,939B2 to Sung (TSMC) entitled “Method and Apparatus for Die Assembly”. Thus, as disclosed in these references, various protective structures such as grooves, sealing rings or other structures, may be provided around edges of the die to protect edges of the dielectric and metallization layers during dicing, and prevent cracking of dielectric layers. However, such structures do not address issues with dicing induced cracking or defect creation in the active regions comprising GaN epi-layers on a silicon substrate, where lattice mismatch creates significant interlayer stresses/strains and misfit dislocations in the GaN epi-layers.
In the field of GaN optoelectronic devices, it is known to pattern the silicon substrate to provide mesa structures, and then form the GaN devices on the mesas. The active regions are thereby raised above the silicon surface and spaced from the scribe lines, so that dicing damage is kept away from the active device regions, e.g. see U.S. Pat. No. 5,874,747 B2 to Redwing et al., entitled “High Brightness Electroluminescent Device Emitting In The Green To Ultraviolet Spectrum And Method Of Making The Same”. Thus, a combination of processing and etching to form devices on mesas with trenches in between, followed by conventional wafer sawing. This reference teaches that growth on reduced area mesas, e.g. 50 μm vs. 200 μm can reduce defect densities. Due to the small area of the mesas, e.g. 170 μm diameter used for LEDs, misfit dislocations due to lattice mismatch can move or migrate to edges of the mesa and annihilate.
However, for large area, high voltage, high current lateral GaN power transistors, such as lateral GaN HEMTs, device sizes are significantly larger, i.e. in the order of millimeters square, e.g. a die size of 6 mm by 2 mm, or 10 mm×10 mm or more. The GaN epi-layer structure is typically several microns thick, e.g. 2 μm to 6 μm and extends over the entire wafer area. The active area of the transistor itself may be surrounded by an inactive region, which may include a protective structure such as a seal ring, as mentioned above. The individual die are typically separated by a dicing street of about 60 μm to 120 μm in width to provide for wafer sawing along a marker or scribe line spaced at least 40 μm from each die. Thus, for GaN power devices with these large die sizes, interlayer stresses/strains between the GaN epi-layers and the silicon substrate can lead to cracking, and dicing induced damage can significantly reduce yield of good die, as well as compromise long term device reliability.
An object of the present invention is to provide a device structure and a method of fabrication for GaN power devices, such as lateral GaN/AlGaN HEMTs, which addresses issues of interlayer stresses which lead to potential cracking and creation of defects in the GaN epi-layers during fabrication, and particularly during wafer dicing, for improved yield and reliability.